ABSTRACT Transistor performance variation and leakage are some of the most critical challenges to the development and effective utilization of nanometer scale CMOS technologies. This talk will describe various sources of transistor variation and techniques for effective characterization of these sources of variation. Topics covered will include design of experiment (DOE) considerations for statistically valid characterization, efficient test structures, test hardware and algorithms, analysis of large volumes of data produced by variability characterization test chips. Case studies to illustrate the methodology and its applications will also be discussed. BIO: Sharad Saxena is a Fellow at PDF Solutions. He received a B.Tech in Computer Science from the Indian Institute of Technology, Kharagpur, India and M.S. and Ph. D. in Computer Science from the University of Massachusetts at Amherst, USA. Prior to joining PDF Solutions, he was a Senior Member of Technical Staff at Texas Instruments’ R&D division in Dallas. His work has been in the area of characterizing, modeling and reducing process variability in semiconductor technologies and its impact on product performance. He has been inventor or co-inventor on 15 issued patents. He has also authored or co-authored 35 papers. The papers have appeared in journals like IEEE Transactions on Electron Devices, IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems, and also in conferences like IEDM, VLSI Technology Symposium, CICC, and International Conference on Microelectronic Test Structures (ICMTS), International Conference on Quality in Electronic Design (ISQED). He was co-author of one of the papers that received the best paper award in ISQED-2004. He was Associate Editor of IEEE Transactions on Computer Aided Design of Electronic Circuits and Systems from Sept 2002-Dec 2005. He has also served on the ISQED program committee. He is a Senior Member of IEEE. Host: Dr. Weiping Shi